In computer systems generally, where a number of independent processors share common-memory resource, it has become widespread practice for each of the independent processors to be provided with a cache memory containing copies of a sub-set of the data contained within the shared memory resource. The sub-set of data retained in the cache is desirably the most commonly-used information by the respective processor, and is used to reduce the number of requests which must be made to the shared memory resource for data to be transferred therefrom.
A number of different mechanisms exist in the prior art for maintaining data within caches and ensuring that relevant data therein is either updated when the shared memory resource is updated, or that the data in the cache is marked as being invalid.
In the latter case, there are a number of different techniques employed. Of particular relevance to the present invention is the cache refreshment mechanism which relies on an ageing criterion to determine at what point data in the cache can no longer be regarded as valid. Typically, when data has been requested by a processor from the shared memory resource, that data is stored in the cache, and its status is marked as valid. After a predetermined period of time, the data is then regarded as no longer valid (known as ageing-out), and its status marked accordingly.
When implementing such ageing mechanisms, it is customary to utilize a state machine to switch cache entries between an idle, invalid state to an alive, valid state when the entry has been retrieved from the shared memory resource, and to switch the entry back to an idle, invalid state once a predetermined period of time has elapsed. The time period may be determined from timers or counters.
It will be appreciated that during the intervening predetermined time period, the data may be requested by the processor any number of times (or even not at all), and may be provided thereto from the cache without reference to the shared memory resource, thus reducing the load thereon.
It will also be appreciated that once data has been "aged-out" of the cache to an idle state, then it is not available for use by the processor, and the shared memory resource must be requested to resupply the data. This inevitably results in a delay to the processor seeking the data, and it is common for a processor to enter a stall condition until the required data has been obtained.